The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention relates to validating continuous signal phase matching in high-speed nets routed as differential pairs.
To reduce costs and delays associated with fabricating circuit boards and packages, designs may be first simulated on a computer. More particularly, computer-aided drafting (CAD) or electronic design automation (EDA) tools may be used to check for design rule violations. Some implementations may provide design rule checks (DRCs) for differential pair signals by end-to-end length matching or length matching per layer. However, differential pair signals may be extensively used in some designs and more accurate and/or efficient DRCs may be required to reduce costs and delays associated with designing such products.